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MC33560 Power Management and Interface IC for Smartcard Readers and Couplers
The MC33560 is an interface IC for smartcard reader/writer applications. It enables the management of any type of smart or memory card through a simple and flexible microcontroller interface. Moreover, several couplers can be coupled in parallel, thanks to the chip select input pin (pin #5). The MC33560 is particularly suited to low power and portable applications because of its power saving features and the minimum of external parts required. Battery life is extended by the wide operating range and the low quiescent current in stand by mode. A highly sophisticated protection system guarantees timely and controlled shutdown upon error conditions. * 100% Compatible with ISO 7816-3 Standard * Wide Battery Supply Voltage Range: 1.8V < VBAT < 6.6V * Programmable VCC Supply for 3V or 5V Card Operation * Power Management for Very Low Quiescent Current in Stand By Mode (30A max) * Microprocessor Wake-up Signal Generated Upon Card Insertion * Self Contained DC/DC Converter to Generate VCC using a Minimum of Passive Components * Controlled Power Up/Down Sequence for High Signal Integrity on the Card I/O and Signal Lines * Programmable Card Clock Generator * Chip Select Capability for Parallel Coupler Operation * High ESD Protection on Card Pins (4kV, Human Body Model) * Fault Monitoring VBATlow, VCClow and ICClim * All Card Outputs Current Limited and Short Circuit Protected * Tested Operating Temperature Range: -25C to +85C
Figure 1. Simplified Functional Block Diagram
VBAT
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24 1
SO-24L DW SUFFIX CASE 751E
TSSOP-24 DTB SUFFIX CASE 948H
24 1
PIN CONNECTIONS
PGND PWRON INT RDYMOD CS RESET IO INVOUT ASYCLKIN 1 2 3 4 5 6 7 8 9 24 ILIM 23 VBAT 22 L1 21 C4 20 C8 19 CRDC8 18 CRDCON 17 CRDDET 16 CRDC4 15 CRDCLK 14 CRDRST 13 CRDVCC (Top View)
SYNCLK 10 L1 ILIM PGND CRDIO 11 DC/DC CONVERTER CRDGND 12
PWRON INT RDYMOD CS SYNCLK ASYCLKIN INVOUT IO RESET C4 C8
POWER MANAGER AND PROGRAMMING CLOCK GENERATOR VBAT
CARD DETECTOR DELAY
CRDDET CRDCON
ORDERING INFORMATION
CRDVCC CRDIO CRDRST CRDC4 CRDC8 CRDCLK CRDGND Device MC33560DW MC33560DWR2 MC33560DTB Package SO-24WB SO-24WB TSSOP-24 Shipping 30 Units/Rail 1000 Tape & Reel 62 Units/Rail 2500 Tape & Reel
LEVEL TRANSLATOR
MC33560DTBR2 TSSOP-24
(c) Semiconductor Components Industries, LLC, 1999
1
October, 1999 - Rev. 0
Publication Order Number: MC33560/D
MC33560
MAXIMUM RATINGS (Note 1)
Rating Battery Supply Voltage Battery Supply Current Power Supply Voltage Power Supply Current Digital Input Pins (2, 4, 5, 6, 7, 9, 10, 17, 18, 20, 21) Digital Output Pins (3, 4, 8) Card Interface Pins (11, 13, 14, 15, 16, 19) Coil Driver Pin (22), ILIM (pin 24) Power Ground (pin 1) ESD Capability: (Note 2) Standard Pins (2, 3, 4, 5, 6, 7, 8, 9, 10, 17, 18, 20, 21, 22, 23, 24) Card Interface Pins (11, 13, 14, 15, 16, 19) SO-24WB Package: Power Dissipation @ TA = 85 C Thermal Resistance Junction to Air TSSOP-24 Package: Power Dissipation @ TA = 85 C Thermal Resistance Junction to Air Operating Ambient Temperature Range Operating Junction Temperature Range Max. Junction Temperature (Note 3) Symbol VBAT IBAT VCC ICC VIN IIN VOUT IOUT VCard ICard IL VESD 2 4 PDs RJAs PDt RJAt TA TJ TJmax 285 140 220 180 - 40 to + 85 - 40 to + 125 150 kV kV mW C/W mW C/W C C C Value 7 200 6 150 - 0.5 to VBAT + 0.5 but < 7 5 - 0.5 to VBAT + 0.5 but < 7 10 - 0.5 to VCC + 0.5 25 200 100 Unit V mA V mA V mA V mA V mA mA
Storage Temperature Range Tstg - 65 to + 150 C Note 1: Maximum electrical ratings are those values beyond which damage to the device may. TA = 25C Note 2: Human body model, R = 1500W, C = 100pF Note 3: Maximum thermal rating beyond which damage to the device may occur This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, input and output voltages should be constrained to the ranges indicated in the recommended operating conditions.
ELECTRICAL CHARACTERISTICS These specifications are written in the same style as common for standard
integrated circuits. The convention considers current flowing into the pin (sink current) as positive and current flowing out of the pin (source current) as negative. (Conditions: VBAT = 4V, VCC = 5V nom, PWRON = VBAT , operating mode, -ICC = 10mA, -25C TA 85C, L1 =47H, RLIM =0W, CRDVCC capacitor=10F, unless otherwise noted.) Characteristic BATTERY POWER SUPPLY SECTION Supply Voltage Range normal operating range extended operating range (Note 4) MC33560 Stand By Quiescent Current PWRON = GND, CRDCON = GND, ASYCLKIN = GND, VBAT = 6V, all other logic inputs and outputs open DC Operating Current -ICC = 10mA ; VCC =5V,VBAT = 6V VBAT undervoltage detection: Upper Threshold Lower Threshold Hysteresis Note 4: See figures 2 and 3. VBAT IoBAT 2.2 1.8 6.0 6.6 30 V Symbol Min Typ Max Unit
ms
mA V
IBATop
12.5
1.6 1.4 0.2
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VCC = 5V NOMINAL POWER SUPPLY SECTION Characteristic Test Conditions
Symbol Min VCC 4.75 4.60 VT5H VT5L VHYS5 -ICClim td -ICCst Vsat22 VFsat22 fsw ISD 80
Guaranteed Limits Typ 5.0 5.0 Max
Unit
Output Voltage
2.2V 1mA 3.0V 1mA
v V v 6V v -IBATv 25mA CC v VBAT v 6V v -ICC v 60mA
V 5.25 5.40 VCC-0.14 4.2 120 80 160 80 50 100 400 120 160 520 4.5 180 V mV mA ms mA mV mV kHz mA
Card VCC Undervoltage Detection: Upper Threshold Lower Threshold Switching Hysteresis Peak Output Current Current limit time-out Start-up Current Low Side Switch Saturation Voltage Rectifier on Saturation Voltage Converter Switching Frequency Shut Down Current (Card access deactivated)
(RDYMOD output) (see table 4)
VCC = 4V, internally limited (RDYMOD = L) VCC = 4V VCC = 2V; 0C to +85C -40C to 0C IL = 50mA, pin 22 IL = 50mA, pin 22 to pin 13 TA = 25 C PWRON = GND, VCC = 2V
VCC = 3V NOMINAL POWER SUPPLY SECTION (VBAT = 2.5V, -ICC = 5mA) Test Conditions Symbol Characteristic
Guaranteed Limits Min Typ 3.0 3.0 Max 3.25 3.40 VCC-0.1 2.4 80 50 50 2.7 110
Unit
Output Voltage
2.2V 1mA 2.5V 1mA
v V BAT v 6V v -ICC v 10mA v V v 6V v -IBATv 50mA CC
VCC 2.75 2.60 VT3H VT3L VHYS3 -ICCst ISD V V V mV mA
Card VCC Undervoltage Detection: Upper Threshold Lower Threshold Switching Hysteresis Start-up Current Shut Down Current (Card access deactivated) Characteristic
(RDYMOD output) (see table 4)
VCC = 2V PWRON = GND, VCC = 2V
APPLICATION INTERFACE DC SECTION (VBAT = 5V) Test Conditions Symbol Min Input High Threshold Voltage (increasing) Input Low Threshold Voltage (decreasing) Switching Hysteresis Threshold Voltage Pull-down resistance Pull-up resistance Output High Voltage pins 2, 4, 5, 6, 10, 17 pins 2, 5, 6, 10 pin 17 pin 4 pins 2, 4, 5, 6, 10, 17 pin 9 pin18 VIN = VBAT -1V, pin 2, 6, 7, 10 VIN = 0.5V, pin 3, 4, 5 IOH = -2.5A, pin 3, pin 4 for CS = H IOH = -50A, pins 7, 20,21 IOH = -0.2mA, pin 8 pin 4 ( in output mode) IOL = 1.0 mA, pins 7, 20, 21 IOL = 0.2mA, pins 3, 4, 8 VIN = 2.5V, CS = H, pins 9, 17, 18, 20, 21 VIH VIL 0.55*VBAT 0.3*VBAT 0.2*VBAT 0.3*VBAT 0.06*VBAT 0.5*VBAT 0.4*VBAT 120 120 VBAT -1 240 240 Guaranteed Limits Typ Max 0.65*VBAT 0.45*VBAT 0.40*VBAT 0.5*VBAT 0.3*VBAT 0.6*VBAT 0.6*VBAT 500 500 V V Unit
VHYST VTH Rdown Rup VOH
V V kW kW V
Output Low Voltage Input Leakage Current
VOL +/-Ileak
0.4 2.0
V
mA
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CARD INTERFACE DC SECTION (VBAT = 5V) Characteristic Test Conditions Symbol Min Output High Voltage Output Low Voltage I/O Pull-up resistance, operating mode, CS =L, PWRON =H Card pins security voltage (Card access deactivated) IOH = -20A, pin 11, 16, 19 IOL = 0.2mA, pins 14, 15 IOL = 1mA, pins 11, 16, 19 IOL = 0.2mA, pins 14, 15 VOL = 0.5V, pin 11, 16, 19 PWRON = GND, lin=10mA, pin 11, 14, 15, 16, 19 Vsecurity VOH VOL 18 2.0 VCC -0.9 0.4 Guaranteed Limits Typ Max V V kW V Unit
Note 5: the transistors T1 on lines IO, C4 and C8 (see figure 24) have a max Rdson of 250W. DIGITAL DYNAMIC SECTION (VBAT = 5V, normal operating mode, Note 6) Guaranteed Limits Characteristic Input Clock Frequency Card Clock Frequency Card Clock Duty Cycle (Note 7) Card Clock Rise and Fall Time I/O Data Transfer Frequency I/O Duty Cycle I/O Rise and Fall Time I/O Transfer Time Card Signal Sequence Interval Card Detection Filter Time: Card insertion Card extraction Internal Reset Delay Ready Delay Time PWRON low Pulse Width RES, VCC power up/down pin 4 CS = L, pin 2 Test Conditions pin 9, duty cycle = 50% pin 15 pin 15, 50% to 50% VCC , fio = 16MHz pin15, 10% 90% VCC pin [7, 11], [21, 16], [20, 19] (Note 8) pin [7, 11], [21, 16], [20, 19] (Note 8) 50% to 50% VCC pin [7, 11], [21, 16], [20, 19] (Note 8) 10% 90% VCC pin [7, 11], [21, 16], [20, 19] (Note 8) 50% to 50% VCC , L H, H L pin 11, 14, 15, 16, 19, VCC power up/down Symbol fasyclk fcrdclk rclk trclk, tfclk fio rio trio, tfio ttr tdseq 0.2 45 1.0 55 150 100 1.0 45 Min Typ Max 20 20 55 10 Unit MHz MHz % ns MHz % ns ns
ms ms ms ms ms ms
tfltin tfltout tdres tdrdy twon
50 50 20
150 150
2.0 2.0
Note 6: Pin loading=30pF, except INVOUT=15pF Note 7: As the clock buffer is optimized for low power consumption and hence not symmetrical, clock signal duty cycle is guaranteed for divide by 2 and divide by 4 ratio. Note 8: In either direction DIGITAL DYNAMIC SECTION (VBAT = 5V, programming mode, Note 6) Guaranteed Limits Characteristic Data Setup Time RDYMOD, PWRON, RESET, IO Data Hold Time RDYMOD, PWRON, RESET, IO CS low Pulse Width Test Conditions pin 2, 4, 6, 7 pin 2, 4, 6, 7 pin 5 Symbol tsmod thmod twcs Min 1.0 1.0 2.0 Typ Max Unit
ms ms ms
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MC33560
Figure 2. Maximum Battery and Card Supply Current vs. VBAT (VCC=5V)
200 180 160 140 I (mA) I (mA) 120 100 80 60 40 20 0 1.5 Mode Sync SYNCLK=4MHz L1=47H Rlim=0 2.5 3.5 4.5 VBAT (V) 5.5 6.5 7.5 ICC MAX IBATop MAX 200 180 160 140 120 100 80 60 40 20 0 1.5 Mode Sync SYNCLK=4MHz L1=47H Rlim=0 2.5 3.5 4.5 VBAT (V) 5.5 6.5 7.5 ICC MAX IBATop MAX
Figure 3. Maximum Battery and Card Supply Current vs. VBAT (VCC=3V)
Figure 4. Battery Current vs. Input Clock Frequency (ICC=0, VBAT=4V)
14 12 10 IBATop (mA) 8 6 4 Async/4 2 0 0 2.0 4.0 6.0 8.0 10 12 14 16 VBAT=4V L1=47H Rlim=0 ICC=0 Async
Figure 5. Battery Current vs. Input Clock Frequency (ICC =0, VBAT=2.5V)
14 12 10 VBAT=2.5V L1=47H Rlim=0 ICC=0
Sync
IBATop (mA)
8 Async 6 Sync 4 Async/2 2 0 0 2.0 4.0 6.0 8.0 10 Async/4 12 14 16
Async/2
Frequency (MHz)
Frequency (MHz)
Figure 6. Maximum Battery Current vs. RLIM (VCC=5V, VBAT=4V)
250 200 IBATop Max (mA) 150 100 50 L1=22H 0 0 1 2 Rlim (ohms) 3 4 5 0 0 Mode Sync SYNCLK=4MHz VBAT=4V 250 200 IBATop Max (mA) 150 100 50
Figure 7. Maximum Battery Current vs. RLIM (VCC=3V, VBAT=2.5V)
L1=100H
L1=100H
Mode Sync SYNCLK=4MHz VBAT=2.5V
L1=47H
L1=47H
L1=22H 1 2 Rlim (ohms) 3 4 5
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Figure 8. Maximum Card Supply Current vs. RLIM (VCC =5V, VBAT =4V)
120 100 ICC Max (mA) 80 60 40 20 0 L1=22H 0 1 2 Rlim (ohms) 3 4 5 L1=47H L1=100H Mode Sync SYNCLK=4MHz VBAT=4V ICC Max (mA) 120 100 80 60 40 20 0 L1=22H 0 1 2 Rlim (ohms) 3 4 5 L1=100H L1=47H Mode Sync SYNCLK=4MHz VBAT=2.5V
Figure 9. Maximum Card Supply Current vs. RLIM (VCC =3V, VBAT =2.5V)
Figure 10. Low Side Switch Saturation Voltage (IL =50mA) vs. Temperature
0.08 Low Side Switch Saturation Voltage (V) 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 -25 -5 15 35 55 75 95 Rectifier On Saturation Voltage (V) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -25
Figure 11. Rectifier On Saturation Voltage (IL =50mA) vs. Temperature
-5
15
35
55
75
95
TA, Ambient Temperature (C)
TA, Ambient Temperature (C)
Figure 12. Card Detection (insertion) filter time vs. Temperature
115 110 tfltout, Filter Time (s) -5 15 35 55 75 95 105 tfltin, Filter Time (s) 100 95 90 85 80 75 70 -25 115 110 105 100 95 90 85 80 75
Figure 13. Card Detection (extraction) filter time vs. Temperature
70 -25
-5
15
35
55
75
95
TA, Ambient Temperature (C)
TA, Ambient Temperature (C)
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Figure 14. Pull Down Resistance vs. Temperature
350 Pull Down Resistance (k W) 330 310 290 270 250 230 210 190 170 150 -25 -5 15 35 55 75 95
TA, Ambient Temperature (C)
Figure 15. Transition from 5V to 3V Card Supply
Figure 16. Transition from 3V to 5V Card Supply
Figure 17. Overcurrent Shutoff (td =160ms)
Figure 18. Undervoltage Shutoff (VT5L=4.6 V)
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Figure 19. Functional Block Diagram
VBAT VBAT VBAT 240 k CS PWRON 240 k VBAT 240 k INT S VBAT 240 k RDYMOD VBATOK POWER MANAGEMENT LOGIC AND PROGRAMMING PROGRAM CARDENABLE Q R FAULT LOGIC CS CARD CRDVCC CS CRDCON PWRON CRDDET VBATOK
t
DELAY 50 mS
CARD PINS SEQUENCER VBAT SEQ1 SEQ2 SEQ3 SEQ4 VBAT IO 240 k SEQ1 CARDENABLE VBATOK VBAT C4 SEQ3 CARDENABLE VBATOK VBAT C8 SEQ3 CARDENABLE VBATOK
FAULT
ON/OFF 3V/5V
DC/DC CONVERTER CRDVCC
ILIM L1 CRDVCC
CRDVCC BIDIRECTIONAL I/O CRDVCC BIDIRECTIONAL I/O CRDVCC BIDIRECTIONAL I/O VBAT CRDVCC
CRDIO
CRDC4
CRDC8
RESET 240 k
DATA LATCH CARDENABLE
LEVEL SHIFT
CRDRST VBAT CRDVCC
LEVEL SHIFT
SEQ4
SYNCLK 240 k ASYCLKIN CLOCK GENERATOR AND PROGRAMMING
CRDCLK
SEQ2 PROGRAM INVOUT
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MC33560
Table 1: PIN FUNCTION DESCRIPTION
Pin Symbol Type Name/Function CONTROLLER INTERFACE 2 3 PWRON INT INPUT pull down OUTPUT pull up This pin is used to start operation of the internal DC/DC converter. In programming mode, this pin is used to set the "Output Voltage" switch. (see table 2). This open collector pin indicates a change in the card presence circuit status. When a card is inserted or extracted, the pin goes to logic level "0". The signal is reset to logic level "1" upon the rising edge of CS or upon the rising edge of PWRON. In the case of a multislot application, two or more INT outputs are connected together and the microcontroller has to poll all the MC33560s to identify which slot was detected. This bidirectional pin has tri-state output and schmitt trigger input. * When RDYMOD is forced to 0, the MC33560 can be set to programming mode by a negative transition on CS. * When RDYMOD is connected to a high impedance, the MC33560 is in normal operating mode, and RDYMOD is in output mode (see tables 2 and 4): - With CS=L and PWRON=H, RDYMOD indicates the status of the DC/DC converter. - With CS=L and PWRON=L, RDYMOD indicates the status of the card detector. This is the MC33560 chip select signal. Pins 2, 6, 7, 10, 20, 21 are disabled when CS=H. When RDYMOD=L, the MC33560 enters programming mode upon the falling edge of CS (see figure 20) The signal present at this input pin is translated to pin 14 (the card reset signal) when CS=L. The signal on this pin is latched when CS=H. This pin is also used in programming mode (see table 2). This pin connects to the Serial I/O port of a microcontroller. A bi-directional level translator adapts the serial I/O signal between the smartcard and the microcontroller. The level translator is enabled when CS=L. The signal on thispin is latched when CS=H. This pin is also used in programming mode. (see table 2) The ASYCLKIN (pin 9) signal is buffered and inverted to generate the output signal INVOUT. This output is used for multislot applications, where the ASYCLKIN inputs and INVOUT outputs are daisy-chained (see the multislot application example in figure 33). This pin can be connected to the microcontroller master clock or any clock signal for asynchronous cards. The signal is fed to the internal clock selector circuit, and is translated to CRDCLK at the same frequency, or divided by 2 or 4, depending on programming (see table 3). This function is used for communication with synchronous cards, and the pin is generally connected to the controller serial interface clock signal. The signal is fed to the internal clock selector circuit, and is translated to CRDCLK upon appropriate programming of the MC33560 (see table 3). When selected at programming, the signal on this pin is latched when CS=H. General purpose input/output. It has the same behavior as I/O, except for programming. It can be connected to abidirectional port of the microcontroller. The level translator is en abled when CS=L, and the signal is latched whenCS=H. (compare with pin 19) General purpose input/output. It has the same behaviour as I/O, except for programming. It can be connected to a bidirectional port of the microcontroller. The level translator is enabled when CS=L, and the signal is latched when CS=H. (compare with pin 16)
4
RDYMOD
I/O & pull up
5
CS
INPUT pull up
6
RESET
INPUT pull down I/O
7
IO
8
INVOUT
CLK OUTPUT CLK INPUT high impedance
9
ASYCLKIN
10
SYNCLK
CLK INPUT pull down
20
C8
I/O
21
C4
I/O
CARD INTERFACE 11 14 15 CRDIO CRDRST CRDCLK I/O OUTPUT OUTPUT This pin connects to the serial I/O pin of the card connector. A bidirectional level translator adapts the serial I/O signal between the card and the microcontroller (compare with pin 7) This pin connects to the RESET pin of the card connector. A level translator adapts the RESET signal driven by the microcontroller (compare with pin 6). This pin connects to the CLK pin of the card connector. The CRDCLK signal is the output of the clock selector circuit.The clock selection is programmed using pins 2, 6 and 7 with RDYMOD forced to "0". General purpose input/output. It has the same behavior as CRDIO. It can be connected to the C4 pin of the card connector. This pin connects to the card detection switch of the card connector. Card detection phase is determined with pin 18. This pin needs an external pull-up or pull-down resistor to operate properly.
16 17
CRDC4 CRDDET
I/O INPUT high impedance
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Pin Symbol Type Name/Function
CARD INTERFACE 18 CRDCON INPUT high impedance I/O This pin connects to PGND or VBAT, or possibly to an output port of the microcontroller. With this pin set to a logic "0", the presence of a card is signalled with a logic "1" on pin 17. With this pin set to a logic "1", the presence of a card is signalled with a logic "0" on pin 17. General purpose input/output. It has the same behavior as CRDIO. It can be connected to the C8 pin of the card connector
19
CRDC8
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CURRENT LIMIT AND THERMAL PROTECTION 1 PGND POWER POWER POWER POWER POWER This pin is the return path for the current flowing into pin 22 (L1). It must be connected to CRDGND using appropriate grounding techniques. 12 13 22 23 CRDGND CRDVCC L1 VBAT This pin is the signal ground. It must be connected to the ground pin of the card connector. It is the reference level for all analog and digital signals. This pin connects to the VCC pin of the card connector. It is the reference level for a logic "1" of pins 11, 14, 15, 16 and 19. This pin connects to an external inductance for the DC/DC converter. Please refer to the description of the DC/DC converter functional block. This pin is connected to the supply voltage. Logic level "1" of pins 2 to 10, 17, 18, 20 and 21 is referenced to VBAT. Operation of the MC33560 is inhibited when VBAT is lower than the minimum value. This pin can be connected to the PGND pin, or to a resistor connected to PGND, or left open, depending on the peak coil current needed to supply the card. 24 ILIM POWER
PROGRAMMING AND STATUS FUNCTIONS The MC33560 features a programming interface and a status interface. Figure 20 shows how to enter and exit programming mode; table 2 shows which pins are used to access the various functions.
Figure 20. MC33560 Programming Sequence
RDYMOD (in) CS PWRON RESET IO ENTER PROGRAMMING MODE PROGRAM DATA VALUE PROGRAM DATA VALUE PROGRAM DATA VALUE LATCH EXIT PROGRAM PROGRAMMING VALUE MODE
Table 2: PIN USE FOR PROGRAMMING AND STATUS FUNCTIONS
Programs CRDVCC TO 3V/5V RDYMOD (in/out) CS (in) PWRON RESET (in) IO (in) Force to 0 rising edge 0/1 Programs CLK input/divide ratio Programs CLK input/divide ratio Select VCC ON/OFF READ 0 0/1 NOT USED NOT USED Select Clock Input Force to 0 rising edge Programs CRDVCC 0/1 0/1 Program ASYCLKIN Divide Ratio Force to 0 rising edge Programs CRDVCC 0/1 0/1 Poll Card Status READ 0 0 or Hi-z NOT USED NOT USED Poll CRDVCC Status READ 0 1 NOT USED NOT USED
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MC33560
CARD VCC AND CARD CLOCK PROGRAMMING The CRDVCC and ASYCLK programming options allow the system clock frequency to be matched to the card clock frequency and to select 3V or 5V CRDVCC supply. Table 3 shows the values of PWRON, RESET and IO for the possible options. The default power reset condition is state 4 (synchronous clock and CRDVCC =5V). All states are latched for each output variable in programming mode at the positive transition of CS (see figure 20).
Table 3 : CARD VCC AND CARD CLOCK TRUTH TABLE
STATE# 0 1 2 3 4 5 6 7 PWRON L L L L H H H H RESET L L H H L L H H IO L H H L L H H L CRDVCC 3V 3V 3V 3V 5V 5V 5V 5V CRDCLK SYNCLK ASYCLKIN/4 ASYCLKIN/2 ASYCLKIN SYNCLK ASYCLKIN/4 ASYCLKIN/2 ASYCLKIN
Note : Card clock integrity is maintained during all frequency commutations (no spikes). State 4 is the default state at power on.
DC/DC CONVERTER AND CARD DETECTOR STATUS The MC33560 status can be polled when CS=L. Please consult table 2 for a description of input and output signals.The significance of the status message is described in table 4.
Table 4 : RDYMOD STATUS MESSAGES
PWRON (input) LOW LOW HIGH HIGH RDYMOD (output) LOW HIGH LOW HIGH Message No card Card present DC/DC converter overload DC/DC converter OK
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DETAILED OPERATING DESCRIPTION
INTRODUCTION
The MC33560 smartcard interface IC has been designed to provide all necessary functions for safe data transfers between a microcontroller and a smartcard or memory card. A card detector scans for the presence of a card and generates a debounced wake-up signal to the microcontroller. Communication and control signal levels are translated between the digital interface and the card interface by the voltage level translator, and the card clock is matched to the system clock frequency by the programmable card clock
CS: FALLING EDGE STAND BY MODE CS = H PWRON = L CS: RISING EDGE RDYMOD: 0 AND CS: FALLING EDGE CS: 1 AND RDYMOD: RISING EDGE PROGRAMMING MODE CS = L RDYMOD = L ACTIVE MODE CS = L PWRON = L CS: 0 AND PWRON: RISING EDGE ISO START SEQUENCE
generator. The power management unit enables the DC/DC converter for card power supply, supervises the power up/down sequence of the card's I/O and signal lines, and keeps the power consumption very low in stand by mode. All card interface pins have adequate ESD protection, and fault monitoring (VBATlow, VCClow, ICClim) guarantees hazard-free card reader operation. Several MC33560s can be operated in parallel, using the same control and data bus, through the use of the chip select signal CS.
Figure 21. MC33560 Operating Modes
ERROR CONDITION ISO STOP SEQUENCE IDLE MODE CS = H PWRON = H CS: 1 AND RDYMOD: RISING EDGE RDYMOD: 0 AND CS: FALLING EDGE PROGRAMMING MODE CS = L RDYMOD = L
PWRON: FALLING EDGE OR ERROR CONDITION
TRANSACTION MODE CS = L PWRON = H
OPERATING MODES
The MC33560 has five operating modes: stand by programming active transaction idle The transitions between these different states are shown in figure 21 above.
STAND BY MODE
Stand by mode allows the MC33560 to detect card insertion and monitor the power supply while keeping the power consumption at a minimum. It is obtained with CS=H and PWRON=L. When the MC33560 detects a card, INT is asserted low to wake up the Microcontroller.
PROGRAMMING MODE
The microcontroller polls the MC33560 by asserting CS=L and reading the RDYMOD pin. If a card is present, the microcontroller starts the DC/DC converter by asserting PWRON=H. This starts the automatic power on sequence: when CRDVcc reaches the undervoltage level (VT5H or VT3H, depending on programming), the card sequencer validates CRDIO, CRDRST, CRDCLK, CRDC4, CRDC8 pins according to the ISO7816-3 sequence (see figure 26). The MC33560 is now in transaction mode, and the system is ready for data exchange via the three I/O lines and the RESET line.
TRANSACTION MODE
The programming mode allows the user to configure the card Vcc and the card clock signal for his specific application. The card supply, CRDVcc, can be programmed to 3V or 5V, and the card clock signal can be defined to be either synchronous, or asynchronous divided by 1, 2 or 4. Programming mode is obtained with RDYMOD=L followed by a negative transition on CS. The programming options are shown in table 3. Programmed values are latched on a positive transition of CS with RDYMOD=L.
ACTIVE MODE
In transaction mode, the MC33560 maintains power and the selected clock signal applied to the card, and the levels of the IO, RESET, C4 and C8 signals between the microcontroller and the card are translated depending on the supply voltages VBAT and VCC. The DC/DC converter status can be monitored on the RDYMOD pin.
IDLE MODE
Idle mode is used when maintaining a card powered up without communicating with it. When an asynchronous clock is used, the selected clock signal is applied to the card
POWER DOWN OPERATION
In active mode, the MC33560 is selected, the RDYMOD pin becomes an output, and the MC33560 status can be polled. Power is not applied to the card.
Power-down can be initiated by the controlling microprocessor, by stopping the DC/DC converter with PWRON=L while CS=L, or by the MC33560 itself when an error condition has been detected (CRDVcc undervoltage, overcurrent longer than 160ms typ., overtemperature, "hot"
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MC33560
card extraction). The communication session is terminated in a given sequence defined in ISO7816-3. The MC33560 then goes into active mode, in which its status can be polled. Stand by mode is reached by deselecting the MC33560
(CS=H).
FUNCTIONAL BLOCKS
CARD DETECTOR
This block monitors the card contact CRDDET (during insertion and extraction), filters the incoming waveform and generates an interrupt signal INT after each change. In order to identify which coupler activated the INT line (multicoupler application) the microcontroller scans both circuits via CS and reads the RDYMOD pin. The programming input CRDCON tells the level detector which type of mechanical contact is implemented (normally open or normally closed). Special care is taken to hold the current consumption very low on this part of the circuit which is continuously powered by the VBAT supply. The CRDDET pin has high impedance input, and an external resistor must be connected to pull-up or pull- down, depending on CRDCON. This resistor is chosen according to the maximum leakage current of the card connector and the PCB. The card detector has an internal 50s debouncing delay. The micro controller has to insert an additional delay (in the ms range) to allow the card contacts to stabilize in the card connector before setting PWRON=H. When the card detector circuit detects a card extraction, it activates the power-down sequence and stops the converter, regardless of the PWRON signal. The 50s delay of the debouncer is enough to ensure that all card signals have reached a safe value before communication with the card takes place.
CARD STATUS
In stand by mode (PWRON=L) the power manager keeps only the "card present" detector alive. All card interface pins are forced to ground potential. In the event of a power-up request from the microcontroller (PWRON L to H transition, CS=L) the power manager starts the DC/DC converter. As soon as the CRDVCC supply reaches the operating voltage range, the circuit activates the card signals in the following sequence: CRDVCC, CRDIO, CRDCLK, CRDC4/C8, CRDRST At the end of the transaction (PWRON reset to L, CS=L) or forced card extraction, the CRDVCC supply powers down and the card signal deactivation sequence takes place: CRDRST, CRDC4/C8, CRDCLK, CRDIO, CRDVCC When CS=L, the bi-directional signal lines (IO, C4 and C8) are put into high impedance state to avoid signal collision with the microcontroller in transmission mode.
BATTERY UNDERVOLTAGE DETECTOR
The task of this block is to monitor the supply voltage, and to allow operation of the DC/DC converter only with valid voltage (typically 1.5 V). The comparator has been designed to have stability better than 20mV in the temperature range.
DC/DC CONVERTER
The controlling microprocessor is informed of the MC33560 status by interrupt and by polling. When a card is extracted or inserted, the INT line is asserted low. The interrupt is cleared upon the rising edge of CS or upon the rising edge of PWRON (INT line set to high state). The microprocessor can poll the status at any time by reading the RDYMOD pin with proper PWRON setting (see tables 2 and 4 ). Since INT and RDYMOD have a high value pull-up resistor (240kW typ.), their rise time can be as long as 10s if parasitic capacitance is high and no other pull-up circuitry is connected.
POWER MANAGER
Upon request from the power manager, the DC/DC converter generates the CRDVCC supply for the smartcard. The output voltage is programmable for 3V or 5V (see table 3) to guarantee full cross compatibility of the reader for 5V and 3V smartcards. The wide voltage supply range, 1.8V < VBAT < 6.6V, accommodates a broad range of coupler applications with different battery configurations (single cell or multiple cells, serial or parallel connections). CRDVCC is current-limited and The short-circuit-proof.To avoid excessive battery loading during a card short-circuit, a current integration function forces the power-down sequence (see figure 28). To retry the session, the microprocessor works through the power on sequence as defined in the power manager section.
DC/DC Converter operating principles
The task of the power manager is to activate only those circuit functions which are needed for a determined operating mode in order to minimize power consumption (see figure 19).
The DC/DC converter architecture used in the MC33560 allows step-up and step-down voltage conversion to be done. The unique regulation architecture permits an automatic transition from step-up to step-down, and from zero to full load, without affecting the output characteristics. DC/DC Converter Description: The converter architecture is very similar to the boost architecture, with an active rectifier in place of the diode. The switching transistor is connected to ground through a resistor network in order to adjust the maximum peak current (see figure 22). A transistor connected to the converter output (CRDVCC) forces this pin to a low voltage when the converter is not operating. This prevents erratic voltage supply to the smartcard when not in use.
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The MC33560 has a built in oscillator; the DC/DC converter requires only one inductor and the output filtering capacitor to operate. Step-Up Operation: When the card supply voltage is lower than the battery voltage, the converter operates like a boost converter; the active rectifier behavior is similar to that of a diode. Step-Down Operation: When the card supply voltage is higher than the battery voltage, the rectifier control circuit puts the power rectifying transistor in conduction when the L1 voltage reaches VBAT+VFSAT22. The voltage across the rectifying transistor is higher than in step-up operation. The efficiency is lower, and similar to a linear regulator. Fault Detection: The DC/DC converter has several features that help to avoid electrical overstress of the MC33560 and of the smartcard, and help to ensure that data transmission with the smartcard occurs only when its supply voltage is within predetermined limits. These functions are: overtemperature detection, current limitation, and card supply undervoltage detection. The level at which current will be limited is defined by the maximum card supply current programmed with the external components L1 and RLIM. The undervoltage detection levels for 3V and 5V card supply are preset internally to the MC33560.
Figure 22. DC/DC Converter Functional Block
VBAT L1 PWN FEED BACK CLOCK OFF STOP ON /OFF ILIMCOMP ON /OFF
DIGITAL FILTER
LOGIC AND COUNTER
Rectifier Switch
CRDVCC Active pull-down switch
Low Side Switch - + 120 mV
RECTIFIER CONTROL
ON /OFF
ON /OFF
CRDGND 2W PGND 0.5 W Internal resistors ILIM RLIM (external) - + VBATOK CONVERTER FAULT +
ERROR AMP.
3V/5V
UNDER VOLTAGE DETECTOR
OVER TEMP DETECTION
CRDGND VREF
-
The overcurrent and undervoltage protection features are complementary, and will shut the circuit off either if the overcurrent is high enough to bring the CRDVCC output below the preset threshold, either after 160ms (typ.) In addition, the DC/DC converter will be allowed to start only if the battery supply voltage is high enough to allow normal operation (1.8V). The undervoltage comparator has a hysteresis and a delay of typically 20ms to ensure stable operation. The current detector is a comparator associated with two resistors: one 2W attached to PGND and usually connected to analog ground, and a 0.5W attached to ILIM, usually connected to ground through an external resistor to adjust the maximum peak current. The voltage developed across this resistor network is then compared to a 120mV (typical) reference voltage, and the comparator output performs a cycle-by-cycle peak current limitation by switching off the low side transistor when the voltage exceeds 120 mV. The internal ILIMCOMP signal is monitored to stop the converter if current limitation is continuously detected
during 160ms (typical). This allows normal operation with high filtering capacitance and low peak current, even at converter start-up. As a result, a short circuit to ground on the card connector or a continuous overcurrent is reported by RDYMOD 160ms (typical) after power up. Unexpected card extraction: The MC33560 detects card extraction and runs a power down sequence if card power is still on when extraction occurs. An active pull-down switch clamps CRDVCC to GND within 150s (max) after extraction is detected. The external capacitors will then be discharged. With typical capacitor values of 10F and 47nF as indicated in the application schematic, the time needed to discharge CRDVCC to a voltage below 0.4V can be estimated to less than 750s. The total time aftercard extraction detection until CRDVCC reaches 0.4V is then estimated to 900s (max). All smartcard connector contacts will be deactivated before CRDVCC deactivation. This ensures that no electrical damage will be caused to the smartcard under abnormal extraction conditions.
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3V/5V programming: It is possible to set the card supply voltage to 3V or 5V at any time, before DC/DC converter start, or during converter operation. When switching from 3V to 5V, a 160ms (typical) delay blanks the undervoltage fault detection to allow filter capacitor charging. PWM: The free-running integrated oscillator has two working modes: variable on-state and fixed frequency (typically 120KHz) for average to heavy loads. variable on-state and variable frequency for light loads. The frequency can be as low as a few kHz if no load is connected to CRDVCC. The charging current of the timing capacitor is related to the VBAT supply voltage, to allow better line regulation, and to increase stability. Filtering Capacitor: A high value allows efficient filtering of card current spikes. Low values allow low start-up charging current. Care must be taken not to combine low capacitor value with high current limiting, as this can generate high ripple. Usual values range from 4.7F to 47F, depending on current limiting. Selecting the external components L1 and RLIM: The choice of inductor L1 and resistor R4 is made by using figure 8 (5V card) and/or figure 9 (3V card) on page 8: First, determine the maximum current that the application requires to supply to the card (ICCmax, on the y-axis) Then, select one curve that crosses the selected ICCmax level. The curve is associated with an inductance value (22H, 47H, or 100H). Finally, use the intersection of the curve and the ICCmax level to find the Rlim value on the x-axis. Good starting values are : L1 =47H; Rlim =0.5W Note also that, for a high inductance value (100H), the filtering capacitor is generally charged before inductance current reaches current limitation, while for alow inductance value, the current limitation is activated after a few converter cycles. Battery requirements: Having determined the L1 and Rlim values, the maximum current drawn from the battery supply is shown by the curves in figures 6 and 7. When the application is powered by a single 3V battery, special care has to be taken to extend its lifetime. When lithium batteries approach the end-of-life, their internal resistance increases, while voltage decreases. This phenomenon can prevent the start-up of the DC/DC converter if the current limiting is set too high, because of the filtering capacitor charging current. CLOCK GENERATOR The primary purpose of the clock generator module is to match the smartcard operating frequency to the system frequency. The source frequency can be provided to ASYCLKIN by the microcontroller itself or from an external oscillator circuit. In programming mode (RDYMOD=L and CS asserted low) the three input variables PWRON, IO and RESET are used to configure the two output variables CRDVCC and CRDCLK as described in table 3. This circuit setup is latched during the positive transition of CS. Furthermore, in asynchronous mode the system clock frequency ASYCLKIN can be divided by a factor of 1, 2 or 4. The circuit controls the frequency commutation to guarantee that the card clock signal remains free from spikes and glitches. In addition, this circuit ensures that CRDCLK signal pulses will not be shorter than the shortest and/or longer than the longest of the clock signals present before and after programming changes . The INVOUT output is provided to drive other circuits without additional load to the microprocessor quartz oscillator. It can also be used to build a local RC oscillator. This driver has been optimized for low consumption; it has no hysteresis, and input levels are not symmetrical. If the ASYCLKIN pin is connected to a sine wave, the duty cycle will not always be 50% at INVOUT.
Clock generator operating principles
Synchronous Clock: This clock is used mainly for memory cards. It can also be used for asynchronous (microprocessor) cards, allowing the use of two different clock sources. The status of SYNCLK is latched at CRDCLK when CS goes high, so that data (the IO pin) and clock are always consistent at the card connector, whatever the CS status is. When using the synchronous clock, the clock output becomes active only when the MC33560 is selected with CS. Asynchronous Clock: This clock is used mainly for microprocessor cards. When applied, the clock output remains active even when the MC33560 is not selected with CS, in order to keep the microprocessor running and avoid an unwanted reset. The ASYCLKIN signal is buffered at the INVOUT pin, so that several MC33560 systems can use the same clock with one load only. Depending on programming, the frequency is fed directly, or divided by 2 or by 4 to the CRDCLK pin. If the duty cycle of the applied clock signal is not exactly symmetrical, it is recommended that the clock signal be divided by two or four to guarantee 50% duty cycle. Clock Signal Synchronization and Consistency (see figure 29). The clock divider includes synchronization logic that controls the switch from synchronous clock to asynchronous (and vice-versa), from any division ratio to any other ratio, during CS changes and at power up. The synchronization logic guarantees that each clock cycle on the CRDCLK pin is finished before changing clock selection (and has always the adequate duration), regardless of the moment the programming is changed. At power-up, when ASYCLKIN is selected, the clock signal at the CRDCLK pin has an entire length, according to the selected divide ratio, whatever the ASYCLKIN signal is versus the internal sequencer timing.
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Figure 23. Clock Generator Functional Block
SYNCLK SYNCHRONISATION LOGIC LATCH CARDENABLE ASYCLKIN INVOUT
SELECTOR
CRDVCC SYNCHRO LATCH CRDCLK SEQ3
B2
B2
RESET IO SELECTOR LATCH
PROGRAM
BIDIRECTIONAL LEVEL TRANSLATOR This module (used on IO/CRDIO, C4/CRDC4, C8/CRDC8, see figure 24) adapts the signal voltage levels of the I/O and control lines between the micro controller (supplied by VBAT) and the smartcard (supplied by CRDVCC) When CS is low, with CRDVCC on, and start sequencing completed, this module is transparent for the data, and acts as if the card was directly connected to the reader microcontroller. The core of the level shifter circuit defined for the bidirectional CRDIO, CRDC4 and CRDC8 lines consists of a NMOS switch which can be driven to the logic low state from either side (microcontroller or card). If both sides work in transmission mode with opposite phase, then signal collision on the line is not avoidable. In this case, the peak current is limited to a safe value for the integrated circuit and the smartcard. During high-to-low transitions, the NMOS transistor impedance (T1=250W max.) is low enough to charge parasitic capacitance, and have a high enough dv/dt. On low to high transition, the NMOS transistor is not active above a certain voltage, and an acceleration circuit is activated to ensure a high dv/dt. When the chip is disabled (CS=H) with the voltage supply CRDVCC still active, the IO, C4 and C8 lines keep their last logic state. When the converter is off, a transistor forces the CRDIO, CRDC4 and CRDC8 lines to a low state, thus preventing any unwanted voltage level to be applied to the data lines when the card is not in use.
Figure 24. Bidirectional Translator Functional Block
VBAT CRDVCC
SECURITY FEATURES The MC33560 has a number of unique security functions to guarantee that no electrical damage will be caused to the smartcard: Battery supply minimum voltage threshold Card supply undervoltage and overcurrent detection with automatic shutdown Card pin overvoltage clamp to CRDVCC Card presence detector for "clean" and fast shut-down Consistent card signal sequencing at start-up and power-down, according to ISO7816, even on error conditions Consistent clock signal, even when division ratio or synchronization clock signal are changed "on the fly" during a card session (see figure 29) Active pull-down on all card pins, including CRDVCC, when not in normal operating mode. A current limiting function and an overtemperature detector are limiting power dissipation. ESD PROTECTION Due to the nature of smartcards, the card interface pins must absorb high ESD (Electro Static Discharge) energy during card insertion. In addition, the control circuits attached to these pins must safely withstand short circuits and voltage transients during forced card extraction. Therefore, the MC33560 features enhanced ESD protection, current limitation and short circuit protection on all smartcard interface pins, including C4 and C8. PARALLEL OPERATION For applications where two or more MC33560 are used, the digital control and data bus lines are common to all MC33560. Only the chip select signal, CS, requires a separate line for each interface. While deselected, all communication pins except CRDCLK will keep their logical state on the card side, and will go to high impedance mode on the microprocessor side. Figure 33 shows a typical application of a dual card reader. This arrangement was chosen only to illustrate the parallel operation of two card interfaces in the same module. The discrete capacitor components are necessary to provide low
18 K IO (C4) (C8) CRDIO (CRDC4) (CRDC8) T2
T1
CONTROL LOGIC
SEQ1 (SEQ3) CARDENABLE
CRDGND
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impedance on the supply lines VBAT and CRDVCC and to suppress the high frequency noise due to the DC/DC converter. The load resistors are external in order to adapt the sense current of the "cardpresent" switches. MINIMUM POWER CONSUMPTION CONSIDERATIONS All analog blocks except the VBAT comparator and the card presence detector are disabled in stand by mode (CS=H: DC/DC converter stopped). In order to maintain stand by current at a minimum value, all pins with pull-up resistance (CS, INT, RDYMOD) have to be kept in the high state or left open, and pins with pull-down resistance (RESET, SYNCLK, PWRON) have to be kept in the low state or left open. ASYCLKIN should not be connected to an active clock signal during stand by to avoid dynamic currents. This is valid also for SYNCLK, except that it can be left open.
Figure 25. Example of single sided PCB layout for MC33560
C8 C4 L1 VBAT ILIM PGND C10 R4 C6 C7 CRDGND CRDIO PWRON INT RDYMOD CS RESET IO SYNCLK ASYCLKIN INVOUT CRDC8 CRDDET CRDC4 CRDCLK CRDRST CRDVCC
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Figure 26. Card Signal Sequence During VCC Power Up/Down
POWER UP NORMAL OPERATION POWER DOWN
CRDVCC CS RDYMOD (out) PWRON IO CLK C4. C8 RESET twon
VTxH
CRDIO CRDCLK CRDC4, CRDC8 CRDRST SEQ1 to SEQ4 SEQ4 to SEQ1 ttr
Figure 27. Interrupt Servicing and Polling
tfltin CRDDET INT CS RDYMOD (out) CS to INT 15 mS typ. INTERRUPT SERVICING
tfltout
tdrdy POLLING INTERRUPT SERVICING POLLING
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MC33560
Figure 28. Card Signal Sequence During VCC Overload and Unexpected Card Extraction
MCU deactivates PWRON after card extraction
poll with PWRON = L -> RDYMOD = H: card still present CS = L, PWRON = H CRDVCC undervoltage -> RDYMOD = L
overload time smaller than tdres (glitch not to scale)
card inserted
tfltin
VTxH VTxL
tfltout
CRDVCC CRDDET INT CS RDYMOD PWRON tdrdy tdres tdres 35 ns typ card extraction
poll with PWRON = L -> RDYMOD = H: card present
MCU polls RDYMOD = H overload time greater than tdres -> converter stop and CRDVCC pull down
poll with PWRON = H -> RDYMOD = L: DC/DC converter overload
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MC33560
Figure 29. "On-the-fly" Card Clock Selection Examples
RDYMOD CS RESET IO SYNCLK ASYCLK CRDCLK
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RDYMOD CS RESET IO SYNCLK ASYCLK CRDCLK
47k C5 10 uF + + C1 Connector 10 uF DB9 U3 C2+ GND C2- VSS RX1 TX1 RX2 TX2 RX3 TX3 C1+ VCC C1- VDD DO1 DI 1 DO2 DI 2 DO3 DI 3 C4 + 10 uF C2 mC reset 10 uF D1 R1 RESET VDD IRQ 0SC1 C3 VPP OSC2 220 nF NC TCAP PA7 PD7 PA6 NC PA5 TCMP PA4 SS PA3 SCLK PA2 MOSI PA1 MISO PA0 RDI PB0 TDO PB1 PC0 PB2 PC1 PB3 PC2 NC PC3 PB4 PC4 PB5 PC5 PB6 PC6 PB7 PC7 VSS NC MC68HC705C9 U1
M1 7805
8..40 VDC Z1
Figure 30. Card Reader/Writer Application
Q1 4 MHz C8 22 pF R3 1M C9 22 pF U2 MC33560 1 - PGND 2 - PWRON 3 - INT 4 - RDYMOD 5 - CS 6 - RESET 7 - IO 8 - INVOUT 9 - ASYCLKIN 10 - SYNCLK 11 - CRDIO 12 - CRDGND ILIM - 24 VBAT - 23 L1 - 22 C4 - 21 C8 - 20 CRDC8 - 19 CRDCON - 18 CRDDET - 17 CRDC4 - 16 CRDCLK - 15 CRDRST - 14 CRDVCC - 13 R4* L1 47 uH
C10 0.1 uF
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MC145407
R2 1M
Card Detect C8
Q1: XTAL 4MHz D1: General Purpose diode R1: 47 kOhm C1, C2, C4,C5: 10 uF R2: 1 MOhm C3: 220 nF L1: MURATA LQH3C 47 uH R3: 1 MOhm C6: 200 nF C7: 10 uF C8, C9: 22 pF M1: 7805 regulator R4: Value depending on max. card current Z1: General Purpose 40 V zener diode U4: Card connector
C4 CLK RST VCC GND I/O U4 Card Slot
C7 C6 10 uF 200 nF
VBAT
MC33560
Card Detect C8
VBAT
mC reset
1 - PGND 2 - PWRON 3 - INT 4 - RDYMOD 5 - CS 6 - RESET 7 - IO 8 - INVOUT 9 - ASYCLKIN 10 - SYNCLK 11 - CRDIO 12 - CRDGND ILIM - 24 VBAT - 23 L1 - 22 C4 - 21 C8 - 20 CRDC8 - 19 CRDCON - 18 CRDDET - 17 CRDC4 - 16 CRDCLK - 15 CRDRST - 14 CRDVCC - 13
C4 CLK RST VCC GND I/O
MC33560
Figure 31. Multi Slot Card Reader/Writer Application
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VBAT
MC33560
RESET VDD IRQ 0SC1 VPP OSC2 NC TCAP PA7 PD7 PA6 NC PA5 TCMP PA4 SS SCLK PA3 MOSI PA2 MISO PA1 RDI PA0 TDO PB0 PC0 PB1 PC1 PB2 PC2 PB3 PC3 NC PC4 PB4 PC5 PB5 PC6 PB6 PC7 PB7 NC VSS
Card Detect C8
1 - PGND 2 - PWRON 3 - INT 4 - RDYMOD 5 - CS 6 - RESET 7 - IO 8 - INVOUT 9 - ASYCLKIN 10 - SYNCLK 11 - CRDIO 12 - CRDGND
ILIM - 24 VBAT - 23 L1 - 22 C4 - 21 C8 - 20 CRDC8 - 19 CRDCON - 18 CRDDET - 17 CRDC4 - 16 CRDCLK - 15 CRDRST - 14 CRDVCC - 13
C4 CLK RST VCC GND I/O
MC33560
PACKAGE DIMENSIONS
(TSSOP-24) DTB SUFFIX PLASTIC PACKAGE CASE 948H-01 ISSUE O
24X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 7.70 7.90 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.303 0.311 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
2X
L/2
24
13
L
PIN 1 IDENT. 1 12
B -U-
0.15 (0.006) T U
S
A -V-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
-W-
DETAIL E N K K1 J1
0.25 (0.010) M
SECTION N-N J
EEE CCC EEE CCC
N F DETAIL E
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MC33560
PACKAGE DIMENSIONS
(SO-24L) DW SUFFIX PLASTIC PACKAGE CASE 751E-04 ISSUE E -A-
24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE X 45 _
M
22X
G
K
DIM A B C D F G J K M P R
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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MC33560/D

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